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ISL43L120, ISL43L121, ISL43L122
Data Sheet November 3, 2004 FN6091.1
Ultra Low ON-Resistance, Single Supply, Dual SPST Analog Switches
The Intersil ISL43L120, ISL43L121, ISL43L122 devices are low ON-resistance, low voltage, bidirectional, precision, dual single-pole/single-throw (SPST) analog switches designed to operate from a single +1.65V to +3.6V supply. Targeted applications include battery powered equipment that benefit from low RON (0.16), low power consumption (0.12W) and fast switching speeds (tON = 13ns, tOFF = 13ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to switch in additional functionality while reducing ASIC design risk. The ISL43L12X are offered in an 8 lead MSOP package, alleviating board space limitations. The ISL43L120, ISL43L121, ISL43L122 are dual singlepole/single-throw (SPST) devices. The ISL43L120 has two normally open (NO) switches; the ISL43L121 has two normally closed (NC) switches; the ISL43L122 has one normally open (NO) and one normally closed (NC) switch and can be used as an SPDT. Table 1 summarizes the performance of this family.
TABLE 1. FEATURES AT A GLANCE ISL43L120 NUMBER OF SWITCHES SW 1/SW 2 1.8V RON 1.8V tON/tOFF 3V RON 3V tON/tOFF PACKAGES 2 NO/NO 0.26 30ns/25ns 0.16 13ns/13ns ISL43L121 2 NC/NC 0.26 30ns/25ns 0.16 13ns/13ns ISL43L122 2 NO/NC 0.26 30ns/25ns 0.16 13ns/13ns
Features
* Low ON Resistance (RON) - V+ = 3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.16 - V+ = 1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.26 * RON Matching Between Channels . . . . . . . . . . . . 0.005 * RON Flatness Over Signal Range . . . . . . . . . . . . . . 0.008 * Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +3.6V * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . <0.12W * Fast Switching Action (V+ = 3.0V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >8kV * 1.8V Logic Compatible (+3V Supply) * Available in 8-Ld thin DFN and 8-Ld MSOP Packages
Applications
* Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
8Ld 3x3 thin DFN, 8Ld MSOP
Related Literature
Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)". Application Note AN557 "Recommended Test Procedures for Analog Switches".
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL43L120, ISL43L121, ISL43L122 Pinouts
(Note 1) ISL43L122 (MSOP, TDFN) TOP VIEW
V+ 1 8 COM1 7 IN 2 6 COM2 5 GND
ISL43L120 (MSOP, TDFN) TOP VIEW
V+ 1 8 COM1 7 IN2
ISL43L121 (MSOP, TDFN) TOP VIEW
V+ 1 8 COM1 7 IN2
NO1 2 IN1 3 NO2 4
NO1 2 IN1 3 NC2 4
NC1 2 IN1 3 NC2 4
6 COM2 5 GND
6 COM2 5 GND
NOTE: 1. Switches Shown for Logic "0" Input.
Ordering Information
(Note 2) TEMP. PART NO. (BRAND) RANGE (C) ISL43L120IU (L120) ISL43L120IR (L10) ISL43L121IU (L121) ISL43L121IR (L11) ISL43L122IU (L122) ISL43L122IR (L12) ISL43L120IUZ * (L120) (Note 3) ISL43L120IRZ * (L10) (Note 3) ISL43L121IUZ * (L121) Note 3 ISL43L121IRZ * (L11) (Note 3) ISL43L122IUZ * (L122) (Note 3) ISL43L122IRZ * (L12) (Note 3) NOTES: 2. Most surface mount devices are available on tape and reel; add "-T" to suffix. 3. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. * Pb-free Parts Coming Soon. -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 PACKAGE 8 Ld MSOP 8 Ld 3x3 thin DFN 8 Ld MSOP 8 Ld 3x3 thin DFN 8 Ld MSOP 8 Ld 3x3 thin DFN 8 Ld MSOP (Pb-free) 8 Ld 3x3 thin DFN (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld 3x3 thin DFN (Pb-free) 8 Ld MSOP (Pb-free) 8 Ld 3x3 thin DFN (Pb-free) PKG. DWG. # M8.118 L8.3x3A M8.118 L8.3x3A M8.118 L8.3x3A M8.118 L8.3x3A M8.118 L8.3x3A M8.118 L8.3x3A
Truth Table
ISL43L120 LOGIC 0 1 NOTE: SW 1, 2 OFF ON ISL43L121 SW 1, 2 ON OFF ISL43L122 SW 1 OFF ON SW 2 ON OFF
Logic "0" 0.5V. Logic "1" 1.4V with a 3V Supply.
Pin Descriptions
PIN V+ GND IN COM NO NC FUNCTION System Power Supply Input (+1.65V to +3.6V) Ground Connection Digital Control Input Analog Switch Common Pin Analog Switch Normally Open Pin Analog Switch Normally Closed Pin
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages IN (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 4) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 300mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . 500mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>8kV
Thermal Information
Thermal Resistance (Typical, Note 5) JA (C/W) 8 Ld 3x3 DFN Package . . . . . . . . . . . . . . . . . . . . . . 110 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 190 Maximum Junction Temperature (Plastic Package). . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300C (Lead Tips Only)
Operating Conditions
Temperature Range ISL43L12XIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 4. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6, 8), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 7) TYP MAX (NOTE 7) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+ See Figure 4 V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at Max RON, Note 10 V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+, Note 11 V+ = 3.3V, VCOM = 0.3, 3V, VNO or VNC = 3V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V 25 Full
0 -3 -60 -3 -80
0.17 0.005 0.008 -
V+ 0.25 0.3 0.02 0.04 0.06 0.07 3 60 3 80
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFlat(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, VIN = 0 to 2.7V, See Figure 1, Note 9 V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF, VIN = 0 to 2.7V, See Figure 1, Note 9 CL = 1.0nF, VG = 0V, RG = 0, See Figure 2 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, See Figure 3 RL = 50, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, See Figure 5
25 Full 25 Full 25 25 25 25
-
15 15 -125 62 -94 182
25 30 25 30 -
ns ns ns ns pC dB dB pF
Turn-OFF Time, tOFF
Charge Injection, Q OFF Isolation Crosstalk (Channel-to-Channel)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 6, 8), Unless Otherwise Specified (Continued) TEST CONDITIONS f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6 f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6 TEMP (C) 25 25 MIN (NOTE 7) TYP 182 290 MAX (NOTE 7) UNITS pF pF
PARAMETER COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 1.65V to 3.6V, VIN = 0V or V+, all channels on or off Full 25 Full 1.65 3.6 30 750 V nA nA
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL NOTES: 6. VIN = input voltage to perform proper function. 7. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. Parts are 100% tested at +25C. Limits across the full temperature range are guaranteed by design and correlation. 9. Guaranteed but not tested. 10. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 11. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. V+ = 3.3V, VIN = 0V or V+ (Note 9) Full Full Full 1.4 -0.5 0.5 0.5 V V A
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6, 8), Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 7) TYP MAX (NOTE 7) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON
Full V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, See Figure 4, Note 9 V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at Max RON, Note 10 V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+, Note 11 V+ = 2.0V, VCOM = 0.3V, 1.8V, VNO or VNC = 1.8V, 0.3V 25 Full 25 Full 25 Full 25 Full V+ = 2.0V, VCOM = 0.3V, 1.8V, or VNO or VNC = 0.3V, 1.8V 25 Full
0 -3 -60 -3 -80
0.26 0.005 0.005 0.074 0.082 -
V+ 0.35 0.4 3 60 3 80
V nA nA nA nA
RON Matching Between Channels, RON RON Flatness, RFLAT(ON)
NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) COM ON Leakage Current, ICOM(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, VIN = 0 to 1.65V, See Figure 1, Note 9 V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF, VIN = 0 to 1.65V, See Figure 1, Note 9 CL = 1.0nF, VG = 0V, RG = 0, See Figure 2
25 Full 25 Full 25
-
30 25 -80
40 45 35 40 -
ns ns ns ns pC
Turn-OFF Time, tOFF
Charge Injection, Q
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.65V to +2.0V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 6, 8), Unless Otherwise Specified (Continued) TEST CONDITIONS RL = 50, CL = 5pF, f = 100kHz, VCOM = 1 VRMS, See Figure 3 and Figure 5 TEMP (C) 25 25 25 25 25 MIN (NOTE 7) TYP 62 -94 182 182 290 MAX (NOTE 7) UNITS dB dB pF pF pF
PARAMETER OFF Isolation Crosstalk (Channel-to-Channel)
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6 COM OFF Capacitance, CCOM(OFF) COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6 f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 6
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 1.65V to 3.6V, VIN = 0V or V+, all channels on or off 25 Full 30 750 nA nA
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VINL Input Voltage High, VINH Input Current, IINH, IINL V+ = 2.0V, VIN = 0V or V+ (Note 9) Full Full Full 1.0 -0.5 0.4 0.5 V V A
Test Circuits and Waveforms
V+ LOGIC INPUT 50% 0V tOFF SWITCH V INPUT NO 90% SWITCH OUTPUT 0V tON SWITCH INPUT VOUT 90% LOGIC INPUT NO or NC COM IN GND RL 50 CL 35pF VOUT tr < 5ns tf < 5ns V+ C
Logic input waveform is inverted for switches that have the opposite logic sense.
Repeat test for all switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES
V+
C
SWITCH OUTPUT VOUT
VOUT
RG
NO or NC
COM
VOUT
V+ LOGIC INPUT ON OFF 0V Q = VOUT x CL ON VG GND IN CL
LOGIC INPUT
FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
FIGURE 2B. TEST CIRCUIT
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122 Test Circuits and Waveforms (Continued)
V+ C SIGNAL GENERATOR RON = V1/100mA
NO or NC NO or NC
V+ C
VNX INX 0V or V+ 1mA V1 IN 0V or V+
ANALYZER RL
COM
COM
GND
GND
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. RON TEST CIRCUIT
V+ C V+ C SIGNAL GENERATOR
NO1 or NC1 COM1
50
NO or NC
IN1 0V or V+ IN2 0V or V+ INX IMPEDANCE ANALYZER
COM
0V or V+
ANALYZER RL
COM2
NO2 or NC2
GND
NC
GND
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43L12X family of devices are bidirectional, single pole/single throw (SPST) analog switches that offer precise switching capability from a single 1.65V to 3.6V supply with low on-resistance (0.16) and high speed operation (tON = 13ns, tOFF = 13ns). The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.65V), low power consumption (2.7W max), low leakage currents (80nA max), and the tiny TDFN and MSOP packaging. The ultra low on-resistance and RON flatness provide very low insertion loss and distortion to application that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 7). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1k resistor in series with the input (see Figure 7). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation.
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122
This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 7). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2V to 3.6V (see Figure 14). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation.
High-Frequency Performance
OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM
In 50 systems, signal response is reasonably flat even past 20MHz with a -3dB bandwidth of 175MHz (see Figure 15). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 16 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 62dB in 50 systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance.
GND OPTIONAL PROTECTION DIODE
FIGURE 7. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL43L12x construction is typical of most single supply CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L12X 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND.
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122 Typical Performance Curves TA = 25C, Unless Otherwise Specified
0.26 ICOM = 100mA 0.24 V+ = 1.8V 0.22 RON () RON () 0.2 0.19 0.18 0.17 0.16 0.15 25C 0.14 0.16 0.14 0.12 V+ = 2.7V V+ = 3V V+ = 3.6V 0.11 0 1 2 VCOM (V) 3 4 0 0.5 1 0.13 0.12 -40C 1.5 VCOM (V) 2 2.5 3 85C V+ = 3V ICOM = 100mA
0.18
FIGURE 8. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SWITCH VOLTAGE
0.3
50 V+ = 1.8V ICOM = 100mA 85C -50
0
V+ = 3V
0.25
RON ()
0.2
Q (pC)
-100
V+ = 1.8V
-40C 0.15
25C
-150
-200
0.1
-250 0 0.5 1 VCOM (V) 1.5 2 0 0.5 1 1.5 VCOM (V) 2 2.5 3
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
80 70 60 50 tON (ns) 40 30 20 10 0 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 -40C 85C
FIGURE 11. CHARGE INJECTION vs SWITCH VOLTAGE
50
40 85C tOFF (ns) 30 -40C 25C
25C
20
10
0
1
1.5
2
2.5 V+ (V)
3
3.5
4
4.5
FIGURE 12. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 13. TURN - OFF TIME vs SUPPLY VOLTAGE
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122 Typical Performance Curves TA = 25C, Unless Otherwise Specified (Continued)
NORMALIZED GAIN (dB) 1.8 1.6 1.4 VINH AND VINL (V) 1.2 VINH 1 0.8 0.6 0.4 0.2 RL = 50 VIN = 0.2VP-P to 2VP-P 1 1.5 2 2.5 V+ (V) 3 3.5 4 4.5 1 10 100 FREQUENCY (MHz) VINL V+ = 3V 0 GAIN
-20 PHASE 0 20 40 60 80 100 600 PHASE (DEGREES)
FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-10 V+ = 3V -20 -30 -40 CROSSTALK (dB) -50 -60 ISOLATION -70 -80 -90 -100 -110 1k 10k 100k 1M 10M CROSSTALK 70 80 90 100 110 100M 500M 20 30 OFF ISOLATION (dB) 40 50 60 10
FIGURE 15. FREQUENCY RESPONSE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 114 PROCESS: Submicron CMOS
FREQUENCY (Hz)
FIGURE 16. CROSSTALK AND OFF ISOLATION
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X A 0.15 C A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A3 b D D2 E E2 e
0.08 C
MIN 0.70 0.25 2.20 1.40 0.25 0.20 -
NOMINAL 0.75 0.20 REF 0.30 3.00 BSC 2.30 3.00 BSC 1.50 0.65 BSC 0.30 8 4
MAX 0.80 0.05 0.35 2.40 1.60 0.40 0.15
NOTES 5,8 7,8 7,8 8 1 2 3 Rev. 2 6/04
E 6 INDEX AREA TOP VIEW B
// A C SEATING PLANE SIDE VIEW
0.10 C
k L L1 N
A3
D2 (DATUM B) 6 INDEX AREA (DATUM A) 1 2 D2/2
7
8
Nd NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389.
L1 10 L
NX L N 8 N-1 e (Nd-1)Xe REF. BOTTOM VIEW (A1) C L NX b 5 0.10 M C A B
NX (b) 5 SECTION "C-C"
9. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. 10. COMPLIANT TO JEDEC MO-229-WEEC-1 except for dimensions E2 & D2.
e TERMINAL TIP FOR EVEN TERMINAL/SIDE
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FN6091.1 November 3, 2004
ISL43L120, ISL43L121, ISL43L122 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03
MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116
MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -CA A2
R1 R
b c D E1
4X
L L1
e E L L1 N R
0.026 BSC 0.187 0.016 8 0.003 0.003 5o 0o 15o 6o 0.199 0.028
0.65 BSC 4.75 0.40 8 0.07 0.07 5o 0o 5.05 0.70
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1 0
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6091.1 November 3, 2004

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